1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to a method of manufacture of a transistor that has a scaled channel length, integrated spacer formation and enhanced silicidation properties.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate insulator and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a "well" exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e., Complementary MOS, "CMOS") are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductors, source/drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features which have less than 0.15 microns critical dimensions. As feature sizes decrease, the size of the resulting transistors as well as the interconnects between transistors also decrease. Smaller transistor size allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow higher speed integrated circuits to be constructed that have greater processing capabilities and that produce less heat.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects ("SCE") generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection ("HCI"). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor.
When decreasing features sizes, the dimensions of transistors must remain proportional. Such a technique is typically referred to as "scaling" of transistors. Various problems exist when reducing feature sizes to create a scaled transistor. One such problem relates to the length of the channel region. The scaling of transistors requires that the length of the channel be decreased proportionally. However, available lithography techniques support a minimum channel length due to their resolution, such minimum channel length not sufficient for desired transistor scaling.
Another problem that presents significant problems relates to surface currents, i.e., currents that may travel from source to gate conductor or from drain to gate conductor. As is known, silicidation steps are commonly taken to increase the conductivity of the surfaces of the gate conductor, source and drain. However, with silicidation employed to increase surface conductivity of the source, drain and gate conductor, the likelihood that current will pass along the surface of the transistor from source to gate or drain to gate increases, particularly as the dimensions of the transistor increase. pacers are generally employed to prevent these surface currents. However, as transistor dimensions continue to increase, creation of satisfactorily performing spacers becomes more difficult.
Thus, there exists a need in the art for a better method for forming transistors that have scaled channel lengths but that resist the flow of surface currents.